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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MC9S08LG32 Rev. 7, 8/2009
MC9S08LG32 Series Covers: MC9S08LG32 and MC9S08LG16
MC9S08LG32
80-LQFP Case 917A 14 mm x 14 mm 64-LQFP Case 840F 10 mm x 10 mm
Features 48-LQFP * 8-bit HCS08 Central Processor Unit (CPU) Case 932 7 mm x 7mm - Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature - On-chip in-circuit emulator (ICE) debug module containing range of -40 C to 85 C and -40 C to 105 C three comparators and nine trigger modes; eight deep FIFO - HCS08 instruction set with added BGND instruction for storing change-of-flow addresses and event-only data; - Support for up to 32 interrupt/reset sources debug module supports both tag and force breakpoints * On-Chip Memory * Peripherals - 32 KB or 18 KB dual array flash; read/program/erase - LCD -- Up to 4 x 41 or 8 x 37 LCD driver with internal over full operating voltage and temperature charge pump. - 1984 byte random access memory (RAM) - ADC -- Up to 16-channel, 12-bit resolution; 2.5 s - Security circuitry to prevent unauthorized access to conversion time; automatic compare function; temperature RAM and flash contents sensor; internal bandgap reference channel; runs in stop3 and * Power-Saving Modes can wake up the system; fully functional from 5.5 V to 2.7 V - Two low-power stop modes (stop2 and stop3) - SCI -- Full duplex non-return to zero (NRZ); LIN master - Reduced-power wait mode extended break generation; LIN slave extended break - Peripheral clock gating register can disable clocks to detection; wakeup on active edge unused modules, thereby reducing currents - SPI -- Full-duplex or single-wire bidirectional; - Low power on-chip crystal oscillator (XOSC) that can double-buffered transmit and receive; master or slave mode; be used in low-power modes to provide accurate clock MSB-first or LSB-first shifting source to real time counter and LCD controller - IIC -- With up to 100 kbps with maximum bus loading; - 100 s typical wakeup time from stop3 mode multi-master operation; programmable slave address; * Clock Source Options interrupt driven byte-by-byte data transfer; supports - Oscillator (XOSC) -- Loop-control Pierce oscillator; broadcast mode and 10-bit addressing crystal or ceramic resonator range of 31.25 kHz to - TPMx -- One 6 channel and one 2 channel; selectable input 38.4 kHz or 1 MHz to 16 MHz capture, output compare, or buffered edge or center-aligned - Internal Clock Source (ICS) -- Internal clock source PWM on each channel module containing a frequency-locked-loop (FLL) - MTIM -- 8-bit counter with match register; four clock controlled by internal or external reference; precision sources with prescaler dividers; can be used for periodic trimming of internal reference allows 0.2% resolution wakeup and 2% deviation over temperature and voltage; supports - RTC -- 8-bit modulus counter with binary or decimal based bus frequencies from 1 MHz to 20 MHz. prescaler; three clock sources including one external source; * System Protection can be used for time base, calendar, or task scheduling - COP reset with option to run from dedicated 1 kHz functions internal clock or bus clock - KBI -- One keyboard control module capable of supporting - Low-voltage warning with interrupt 8 x 8 keyboard matrix - Low-voltage detection with reset - IRQ -- External pin for wakeup from low-power modes - Illegal opcode detection with reset * Input/Output - Illegal address detection with reset - 39, 53, or 69 GPIOs - Flash and RAM protection - 8 KBI and 1 IRQ interrupt with selectable polarity * Development Support - Hysteresis and configurable pullup device on all input pins; - Single-wire background debug interface configurable slew rate and drive strength on all output pins. - Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints * Package Options - 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP in on-chip debug module)
Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. (c) Freescale Semiconductor, Inc., 2009. All rights reserved.
Table of Contents
1 2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10 2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10 2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11 2.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12 2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .17 2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .22 2.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .24 2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .30 2.11.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.12 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35 2.14.2 Conducted Transient Susceptibility . . . . . . . . . .35 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .39 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.1.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.1.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Figure 17.Internal Oscillator Deviation from Trimmed Frequency 25 Figure 18.ADC Input Impedance Equivalency Diagram. . . . . . . 26 Figure 19.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 20.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 21.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 22.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 30 Figure 23.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 32 Figure 24.SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . 32 Figure 25.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 33 Figure 26.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 33 Figure 27.4 MHz, Positive Polarity Pins 1 - 41 . . . . . . . . . . . . . 36 Figure 28.4 MHz, Positive Polarity Pins 42 - 80 . . . . . . . . . . . . 36 Figure 29.4 MHz, Negative Polarity Pins 1 - 41. . . . . . . . . . . . . 37 Figure 30.4 MHz, Negative Polarity Pins 42 - 80. . . . . . . . . . . . 37 Figure 31.Device Number Example for Auto Parts. . . . . . . . . . . 39 Figure 32.Device Number Example for IMM Parts. . . . . . . . . . . 39 Figure 33.80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 34.64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 35.48-pin LQFP Package Drawing (Case 932, Doc #98ASH00962A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3 4
List of Tables
Table 1. MC9S08LG32 Series Features by MCU and Package . 4 Table 2. Pin Availability by Package Pin-Count . . . . . . . . . . . . . . 8 Table 3. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 11 Table 5. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. ESD and Latch-Up Test Conditions . . . . . . . . . . . . . . . 12 Table 7. ESD and Latch-Up Protection Characteristics. . . . . . . 13 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 17 Table 10.Oscillator Electrical Specifications (Temperature Range = -40 C to 105 C Ambient) . . . . . . . . . . . . . . . . . . . . . 22 Table 11.ICS Frequency Specifications (Temperature Range = -40 C to 105 C Ambient) . . . . . . . . . . . . . . . . . . . . . 24 Table 12.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 25 Table 13.12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 17.LCD Electricals, 3 V Glass . . . . . . . . . . . . . . . . . . . . . 34 Table 18.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 19.Radiated Emissions, Electric Field . . . . . . . . . . . . . . . 35 Table 20.Conducted Susceptibility, EFT/B . . . . . . . . . . . . . . . . . 35 Table 21.Susceptibility Performance Classification . . . . . . . . . . 38 Table 22.Device Numbering System . . . . . . . . . . . . . . . . . . . . . 38 Table 23.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5
List of Figures
Figure 1. MC9S08LG32 Series Block Diagram . . . . . . . . . . . . . . 3 Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 64-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Typical Low-side Drive (sink) characteristics - High Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Typical Low-side Drive (sink) characteristics - Low Drive (PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Typical High-side Drive (source) characteristics - High Drive (PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Typical High-side Drive (source) characteristics - Low Drive (PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. Typical Run IDD for FBE Mode at 1 MHz. . . . . . . . . . . 19 Figure 10.Typical Run IDD for FBE Mode at 20 MHz . . . . . . . . . 20 Figure 11.Typical Run IDD for FEE Mode at 1 MHz . . . . . . . . . . 20 Figure 12.Typical Run IDD for FEE Mode at 20 MHz . . . . . . . . . 21 Figure 13.Typical Stop2 IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14.Typical Stop3 IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15.Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16.Typical Crystal or Resonator Circuit: Low Range/Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MC9S08LG32 Series Data Sheet, Rev. 7 2 Freescale Semiconductor
HCS08 CORE
PORT A
CPU
INT BKGD/MS
ON-CHIP ICE (ICE) and DEBUG MODULE (DBG) Real Time Counter (RTC) Modulo Timer (MTIM) TMRCLK
PORT B
BKGD
BKP
LCD28/ADC5/TPMCLK/PTA7 LCD27/ADC4/TPM2CH1/KBI7/PTA6 LCD26/ADC3/TPM2CH0/KBI6/PTA5 LCD25/ADC2/RX2/KBI5/PTA4 LCD24/ADC1/TX2/KBI4/PTA3 LCD23/ADC0/SDA/PTA2 LCD22/SCL/PTA1 LCD21/PTA0 LCD[40:37]/PTB[7:4] LCD[32:29]/PTB[3:0]
HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT
COP IRQ LVD
RESET IRQ
SERIAL PERIPHERAL INTERFACE (SPI)
SS SPSCK MISO
MOSI
SCL USER FLASH A (LG32 = 16K BYTES) (LG16 = 2K BYTES) IIC MODULE (IIC) SDA TPM2CH[5:0] TPMCLK TPM1CH[1:0] TPMCLK
PORT D
PORT C
8-BIT KEYBOARD INTERRUPT (KBI)
KBI[7:0]
RESET/PTC6 BKGD/MS/PTC5 LCD[20:16]/PTC[4:0]
LCD[7:0]/PTD[7:0]
6-CHANNEL TIMER/PWM (TPM2)
PORT E
LCD[15:8]/PTE[7:0]
USER FLASH B (LG32 = 16K BYTES) (LG16 = 16K BYTES)
2-CHANNEL TIMER/PWM (TPM1) SERIAL COMMUNICATIONS INTERFACE (SCI1) SERIAL COMMUNICATIONS INTERFACE (SCI2) XTAL
TxD1
RxD1
USER RAM
1984 BYTES
TxD2
RxD2
PORT G
EXTAL/PTF7 XTAL/PTF6 TPM2CH3/KBI2/MOSI/PTF5 TPM2CH4/KBI1/MISO/PTF4 TPM2CH5/KBI0/SS/PTF3 ADC14/IRQ/TPM1CH1/SPSCK/PTF2 ADC13/TPM1CH0/RX1/PTF1 ADC12/TPM2CH2/KBI3/TX1/PTF0 LCD[44:41]/PTG[7:4] LCD[36:33]/PTG[3:0]
INTERNAL CLOCK Source (ICS) LOW-POWER OSCILLATOR
VLL3_2
EXTAL 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC)
PORT H
PORT F
VLL3 VLL1 VLL2 VCAP1 VCAP2 LCD[44:0] VDD VSS VSS2 LIQUID CRYSTAL DISPLAY DRIVER (LCD)
AD[15:0]
TPM2CH4/KBI1/PTH7 ADC15/KBI0/TPM2CH5/PTH6 ADC11/TPM1CH0/KBI3/TX1/PTH5 ADC10/TPM1CH1/KBI2/RX1/PTH4 ADC[9:6]/KBI[7:4]/PTH[3:0] SS/SCL/TPM2CH0/PTI5 SPSCK/SDA/TPM2CH1/PTI4 MOSI/TPM2CH2/PTI3 MISO/TPM2CH3/PTI2 TX2/TMRCLK/PTI1 RX2/PTI0
VOLTAGE REGULATOR
VDDA/VREFH VSSA/VREFL
Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/*
Figure 1. MC9S08LG32 Series Block Diagram
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 3
PORT I
Pin Assignments
Table 1. MC9S08LG32 Series Features by MCU and Package
Feature Flash size (bytes) RAM size (bytes) Pin quantity ADC LCD ICE + DBG ICS IIC IRQ KBI GPIOs RTC MTIM SCI1 SCI2 SPI TPM1 channels TPM2 channels XOSC 69 53 80 16 ch 8 x 37 4 x 41 64 12 ch 8 x 29 4 x 33 MC9S08LG32 32,768 1984 48 9 ch 8 x 21 4 x 25 yes yes yes yes 8 pin 39 yes yes yes yes yes 2 6 yes 53 39 64 12 ch 8 x 29 4 x 33 48 9 ch 8 x 21 4 x 25 MC9S08LG16 18,432
1
Pin Assignments
This section shows the pin assignments for the MC9S08LG32 series devices. The priority of functions on a pin is in ascending order from left to right and bottom to top. Another view of pinouts and function priority is given in Table 2.
MC9S08LG32 Series Data Sheet, Rev. 7 4 Freescale Semiconductor
Pin Assignments
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
PTE0/LCD8 PTE1/LCD9 PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTG0/LCD33 PTG1/LCD34 PTG4/LCD41 PTG5/LCD42 PTG6/LCD43 PTG7/LCD44 VLL3_2 VSS2 PTE6/LCD14 PTE7/LCD15 PTC0/LCD16 PTC1/LCD17 PTC2/LCD18 PTC3/LCD19
VREFH/VREFL are internally connected to VDDA/VSSA.
Freescale Semiconductor
VLL3 PTF5/MOSI/KBI2/TPM2CH3 PTF4/MISO/KBI1/TPM2CH4 PTI5/TPM2CH0/SCL/SS PTI4/TPM2CH1/SDA/SPSCK PTI3/TPM2CH2/MOSI PTI2/TPM2CH3/MISO PTI1/TMRCLK/TX2 PTI0/RX2 PTH7/KBI1/TPM2CH4 VSS VDD PTF7/EXTAL PTF6/XTAL VDDA/VREFH VSSA/VREFL PTH6/TPM2CH5/KBI0/ADC15 PTF2/SPSCK/TPM1CH1/IRQ/ADC14 PTF1/RX1/TPM1CH0/ADC13 PTF0/TX1/KBI3/TPM2CH2/ADC12
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTB3/LCD32 PTB2/LCD31 PTB7/LCD40 PTB6/LCD39 PTB5/LCD38 PTB4/LCD37 PTB1/LCD30 PTB0/LCD29 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
80-Pin LQFP
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
PTC4/LCD20 PTA0/LCD21 PTG2/LCD35 PTG3/LCD36 PTA1/SCL/LCD22 PTA2/SDA/ADC0/LCD23 PTA3/KBI4/TX2/ADC1/LCD24 PTA4/KBI5/RX2/ADC2/LCD25 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTA7/TPMCLK/ADC5/LCD28 PTC5/BKGD/MS PTC6/RESET PTH0/KBI4/ADC6 PTH1/KBI5/ADC7 PTH2KBI6/ADC8 PTH3/KBI7/ADC9 PTH4/RX1/KBI2/TPM1CH1/ADC10 PTH5/TX1/KBI3/TPM1CH0/ADC11 PTF3/SS/KBI0/TPM2CH5
Figure 2. 80-Pin LQFP
NOTE
MC9S08LG32 Series Data Sheet, Rev. 7 5
Pin Assignments
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PTE0/LCD8 PTE1/LCD9 PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTG0/LCD33 PTG1/LCD34 VLL3_2 VSS2 PTE6/LCD14 PTE7/LCD15 PTC0/LCD16 PTC1/LCD17 PTC2/LCD18 PTC3/LCD19
VREFH/VREFL are internally connected to VDDA/VSSA.
6
VLL3 PTF5/MOSI/KBI2/TPM2CH3 PTF4/MISO/KBI1/TPM2CH4 PTI5/TPM2CH0/SCL/SS PTI4/TPM2CH1/SDA/SPSCK PTH7/KBI1/TPM2CH4 VSS VDD PTF7/EXTAL PTF6/XTAL VDDA/VREFH VSSA/VREFL PTH6/TPM2CH5/KBI0/ADC15 PTF2/SPSCK/TPM1CH1/IRQ/ADC14 PTF1/RX1/TPM1CH0/ADC13 PTF0/TX1/KBI3/TPM2CH2/ADC12
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTB3/LCD32 PTB2/LCD31 PTB1/LCD30 PTB0/LCD29 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
64-Pin LQFP
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
PTC4/LCD20 PTA0/LCD21 PTG2/LCD35 PTG3/LCD36 PTA1/SCL/LCD22 PTA2/SDA/ADC0/LCD23 PTA3/KBI4/TX2/ADC1/LCD24 PTA4/KBI5/RX2/ADC2/LCD25 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTA7/TPMCLK/ADC5/LCD28 PTC5/BKGD/MS PTC6/RESET PTH4/RX1/KBI2/TPM1CH1/ADC10 PTH5/TX1/KBI3/TPM1CH0/ADC11 PTF3/SS/KBI0/TPM2CH5
Figure 3. 64-Pin LQFP
NOTE
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor
Pin Assignments
PTC0/LCD16
PTC1/LCD17
PTC2/LCD18 38
PTE2/LCD10
PTE3/LCD11
PTE0/LCD8
PTE1/LCD9
48 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 12 14 13 PTF7/EXTAL VSS PTF4/MISO/KBI1/TPM2CH4 VDDA/VREFH PTF2/SPSCKS/TPM1CH1/IRQ/ADC14 PTF1/RX1/TPM1CH0/ADC13 VLL3 PTF5/MOSI/KBI2/TPM2CH3 PTF6/XTAL VSSA/VREFL VDD 15 16 17 18 19 20 21 22 23 1 2 3 4 5 6 7 8 9 10 11 48-Pin LQFP 47 46 45 44 43 42 41 40 39
37 36 PTC4/LCD20 35 34 33 32 31 30 29 28 27 26 PTA0/LCD21 PTA1/SCL/LCD22 PTA2/SDA/ADC0/LCD23 PTA3/KBI4/TX2/ADC1/LCD24 PTA4/KBI5/RX2/ADC2/LCD25 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTA7/TPMCLK/ADC5/LCD28 PTC5/BKGD/MS PTC6/RESET 25 PTF3/SS/KBI0/TPM2CH5 24 PTF0/TX1/KBI3/TPM2CH2/ADC12
Figure 4. 48-Pin LQFP
NOTE
VREFH/VREFL are internally connected to VDDA/VSSA.
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 7
PTC3/LCD19
PTE4/LCD12
PTE5/LCD13
PTE6/LCD14
PTE7/LCD15
Pin Assignments
Table 2. Pin Availability by Package Pin-Count
Packages 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 1 2 3 4 5 6 7 8 -- -- -- -- 9 10 11 12 13 14 15 16 17 18 19 20 21 -- -- -- -- 22 23 24 25 26 27 28 29 30 48 1 2 3 4 5 6 -- -- -- -- -- -- -- -- 7 8 9 10 11 12 13 14 15 -- -- -- -- -- -- -- 16 17 18 19 20 21 -- 22 Port Pin PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTB3 PTB2 PTB7 PTB6 PTB5 PTB4 PTB1 PTB0 PTD1 PTD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 PTF5 PTF4 PTI5 PTI4 PTI3 PTI2 PTI1 PTI0 PTH7 VSS VDD PTF7 PTF6 VDDA VSSA PTH6 PTF2 Alt 1 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD32 LCD31 LCD40 LCD39 LCD38 LCD37 LCD30 LCD29 LCD1 LCD0 -- -- -- -- -- MOSI MISO TPM2CH0 TPM2CH1 TPM2CH2 TPM2CH3 TMRCLK RX2 KBI1 -- -- EXTAL XTAL VREFH VREFL TPM2CH5 SPSCK <-- Lowest Priority Alt 2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- KBI2 KBI1 SCL SDA MOSI MISO TX2 -- TPM2CH4 -- -- -- -- -- -- KBI0 TPM1CH1 --> Highest Alt 3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- TPM2CH3 TPM2CH4 SS SPSCK -- -- -- -- -- -- -- -- -- -- -- ADC15 IRQ Alt 4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ADC14
MC9S08LG32 Series Data Sheet, Rev. 7 8 Freescale Semiconductor
Pin Assignments
Table 2. Pin Availability by Package Pin-Count (continued)
Packages 80 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 64 31 32 33 34 35 -- -- -- -- 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 -- -- -- -- 57 58 59 60 48 23 24 25 -- -- -- -- -- -- 26 27 28 29 30 31 32 33 34 -- -- 35 36 37 38 39 40 41 42 -- -- -- -- -- -- -- -- 43 44 Port Pin PTF1 PTF0 PTF3 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 PTC6 PTC5 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTG3 PTG2 PTA0 PTC4 PTC3 PTC2 PTC1 PTC0 PTE7 PTE6 VSS2 VLL3_2 PTG7 PTG6 PTG5 PTG4 PTG1 PTG0 PTE5 PTE4 Alt 1 RX1 TX1 SS TX1 RX1 KBI7 KBI6 KBI5 KBI4 RESET BKGD/MS TPMCLK KBI7 KBI6 KBI5 KBI4 SDA SCL LCD36 LCD35 LCD21 LCD20 LCD19 LCD18 LCD17 LCD16 LCD15 LCD14 -- -- LCD44 LCD43 LCD42 LCD41 LCD34 LCD33 LCD13 LCD12 <-- Lowest Priority Alt 2 TPM1CH0 KBI3 KBI0 KBI3 KBI2 ADC9 ADC8 ADC7 ADC6 -- -- ADC5 TPM2CH1 TPM2CH0 RX2 TX2 ADC0 LCD22 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --> Highest Alt 3 ADC13 TPM2CH2 TPM2CH5 TPM1CH0 TPM1CH1 -- -- -- -- -- -- LCD28 ADC4 ADC3 ADC2 ADC1 LCD23 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Alt 4 -- ADC12 -- ADC11 ADC10 -- -- -- -- -- -- -- LCD27 LCD26 LCD25 LCD24 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 9
Electrical Characteristics
Table 2. Pin Availability by Package Pin-Count (continued)
Packages 80 77 78 79 80 64 61 62 63 64 48 45 46 47 48 Port Pin PTE3 PTE2 PTE1 PTE0 Alt 1 LCD11 LCD10 LCD9 LCD8 <-- Lowest Priority Alt 2 -- -- -- -- --> Highest Alt 3 -- -- -- -- Alt 4 -- -- -- --
2
2.1
Electrical Characteristics
Introduction
This section contains electrical and timing specifications for the MC9S08LG32 series of microcontrollers available at the time of publication.
2.2
Parameter Classification
Table 3. Parameter Classifications
P C Those parameters are guaranteed during production testing on each individual device. Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. Those parameters are derived mainly from simulations.
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
T
D
NOTE
The classification is shown in the column labeled "C" in the parameter tables where appropriate.
2.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry that protects against damage due to high static voltage or electrical fields. However, it is advised that normal precautions should be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
MC9S08LG32 Series Data Sheet, Rev. 7 10 Freescale Semiconductor
Electrical Characteristics
Table 4. Absolute Maximum Ratings
Rating Supply voltage Maximum current into VDD Digital input voltage Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 Storage temperature range
1
Symbol VDD IDD VIn ID Tstg
Value -0.3 to +5.8 120 -0.3 to VDD + 0.3 25 2 -55 to 150
Unit V mA V mA C
Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages and use the largest of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in an external power supply going out of regulation. Ensure that the external VDD load will shunt current greater than maximum injection current, this will be of greater risk when the MCU is not consuming power. For instance, If no system clock is present, or if the clock rate is very low (which would reduce overall power consumption).
2.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics
Rating Operating temperature range (packaged) Maximum junction temperature Thermal resistance Single-layer board 80-pin LQFP 64-pin LQFP 48-pin LQFP Thermal resistance Four-layer board 80-pin LQFP 64-pin LQFP 48-pin LQFP Symbol TA TJ Value TL to TH -40 to +105 125 Unit C C
JA
61 71 80
C/W
JA
48 52 56
C/W
The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD x JA)
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 11
Eqn. 1
Electrical Characteristics
where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint + PI/O Pint = IDD x VDD, Watts -- chip internal power PI/O = Power dissipation on input and output pins -- user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273 C) Solving Equation 1 and Equation 2 for K gives: K = PD x (TA + 273 C) + JA x (PD)2 Eqn. 3 Eqn. 2
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA.
2.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for automotive grade integrated circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 6. ESD and Latch-Up Test Conditions
Model Description Symbol R1 C -- -- -- Value 1500 100 3 -2.5 7.5
Unit
pF -- V V
Human Body Series resistance Model Storage capacitance Number of pulses per pin Latch-up Minimum input voltage limit Maximum input voltage limit
MC9S08LG32 Series Data Sheet, Rev. 7 12 Freescale Semiconductor
Electrical Characteristics
Table 7. ESD and Latch-Up Protection Characteristics
No. 1 2 3
1
Rating1 Human body model (HBM) Charge device model (CDM) Latch-up current at TA = 85 C
Symbol VHBM VCDM ILAT
Min 2500 750 100
Max -- -- --
Unit V V mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted.
2.6
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics. Table 8. DC Characteristics
Num C 1 2 -- Operating Voltage P Output high voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = -2 mA 3 V, ILoad = -0.6 mA Output high voltage -- High Drive (PTxDSn = 1) V 5 V, ILoad = -10 mA 3 V, ILoad = -3 mA 3 P Output low voltage -- Low Drive (PTxDSn = 0) 5 V, ILoad = 2 mA 3 V, ILoad = 0.6 mA Output low voltage -- High Drive (PTxDSn = 1) 5 V, ILoad = 10 mA 3 V, ILoad = 3 mA 4 P Output high current -- Max total IOH for all ports 5V 3V 5 C Output high current -- Max total IOL for all ports 5V 3V 6 7 8 9 10 11 12 13 P Bandgap voltage reference P Input high voltage; all digital inputs P Input low voltage; all digital inputs P Input hysteresis; all digital inputs P Input leakage current; input only pins
2
Characteristic
Symbol -- VOH
Min 2.7 VDD - 0.8 VDD - 0.8 VDD - 0.8 VDD - 0.8
Typ1 -- -- -- -- -- -- -- -- --
Max 5.5 -- -- -- --
Unit V V
VOL
-- 0.8 0.8 0.8 0.8
V
IOHT
--
-- 100 60
mA
IOLT
--
-- 100 60
mA
VBG VIH VIL Vhys |IIn| VIn = VDD or VSS |IOZ| VIn = VDD or VSS RPU
-- 0.65 x VDD -- 0.06 x VDD -- -- 20 20
1.225
--
V V V mV A A k k
--
-- -- 0.1 0.1 45 45
--
0.35 x VDD -- 1 1 65 65
P High impedence (off-state) leakage current P Internal pullup resistors3 P Internal pulldown resistors
4
RPD
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 13
Electrical Characteristics
Table 8. DC Characteristics (continued)
Num C 14 D DC injection current 5, 6, 7 VIN < VSS, VIN > VDD Characteristic Single pin limit Total MCU limit, includes sum of all stressed pins CIn VRAM VPOR tPOR VLVD1 VDD falling VDD rising 20 P Low-voltage detection threshold -- low range VDD falling VDD rising 21 P Low-voltage warning threshold -- high range 1 VDD falling VDD rising 22 P Low-voltage warning threshold -- high range 0 VDD falling VDD rising 23 P Low-voltage warning threshold -- low range 1 VDD falling VDD rising 24 P Low-voltage warning threshold -- low range 0 VDD falling VDD rising 25 P Low-voltage inhibit reset/recover hysteresis 5V 3V
1 2 3 4 5 6 7
Symbol IIC
Min -- --
Typ1 -- --
Max 2 25
Unit mA mA
15 16 17 18 19
C Input Capacitance, all non-supply pins C RAM retention voltage P POR rearm voltage D POR rearm time P Low-voltage detection threshold -- high range
-- 2 0.9 10 3.9 4.0
-- -- 1.4 -- 4.0 4.1 2.56 2.62 4.6 4.7 4.3 4.4 2.92 2.98 2.74 2.80 100 60
8 -- 2.0 -- 4.1 4.2
pF V V s V
VLVD0 2.48 2.54 VLVW3 4.5 4.6 VLVW2 4.2 4.3 VLVW1 2.84 2.90 VLVW0 2.66 2.72 Vhys -- 2.82 2.88 -- 3.00 3.06 4.4 4.5 4.7 4.8 2.64 2.70
V
V
V
V
V
mV
Typical values are measured at 25 C. Characterized, not tested Measured with VIn = VDD or VSS. Measured with VIn = VSS. Measured with VIn = VDD. All functional non-supply pins, except for PTC6 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. For instance, if no system clock is present, or if clock rate is very low (which would reduce overall power consumption).
MC9S08LG32 Series Data Sheet, Rev. 7 14 Freescale Semiconductor
Electrical Characteristics
Typical VOL vs. IOL AT VDD = 5V
0.80 0.70 0.60
Typical V OL vs. IOL AT V DD = 3V
1.40 1.20 1.00 Hot (105C) Room (25C) Cold (-40C)
Hot (105C) Room (25C) Cold (-40C)
VOL (v)
VOL (v)
0.50 0.40 0.30 0.20 0.10 0.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0.80 0.60 0.40 0.20 0.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13
IOL (mA)
IOL (mA)
Figure 5. Typical Low-side Drive (sink) characteristics - High Drive (PTxDSn = 1)
Typical VOL vs. IOL A VDD = 5V T
0.90 0.80 0.70 0.60
Typical VOL vs. IOL AT VDD = 3V
0.90 0.80 0.70 0.60 Hot (105C) Room (25C) Cold (-40C)
Hot (105C) Room (25C) Cold (-40C)
VOL (v)
VOL (v)
0.50 0.40 0.30 0.20 0.10 0.00 0 1 2 3 4 5
0.50 0.40 0.30 0.20 0.10 0.00 0 1 2 3
IOL (mA)
IOL (mA)
Figure 6. Typical Low-side Drive (sink) characteristics - Low Drive (PTxDSn = 0)
Typical VDD - VOH vs. IOH AT VDD = 5V
0.8 0.6 0.4 0.2 0.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15
1.2
Typical VDD - VOH vs. IOH AT VDD=3V
Hot (105C) Room (25C) Cold (-40C)
Hot (105C)
VDD - VOH (v)
VDD - VOH (v)
Room (25C) Cold (-40C)
1.0 0.8 0.6 0.4 0.2 0.0 0 -1
IOH (mA)
-2
-3
-4
-5
IOH (mA)
-6
-7
-8
-9 -10 -11 -12 -13
Figure 7. Typical High-side Drive (source) characteristics - High Drive (PTxDSn = 1)
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 15
Electrical Characteristics
Typical VDD - VOH vs. IOH AT VDD = 5V
1.2 1.0
Typical VDD - VOH vs. IOH AT VDD=3V
1.2
Hot (105C) Room (25C) Cold (-40C)
Hot (105C) Room (25C)
1.0
VDD - VOH (v)
-2 -3 -4 -5
VDD - VOH (v)
0.8 0.6 0.4 0.2 0.0
0
Cold (-40C)
0.8 0.6 0.4 0.2 0.0
-1
0
-1
IOH (mA)
IOH (mA)
-2
-3
Figure 8. Typical High-side Drive (source) characteristics - Low Drive (PTxDSn = 0)
MC9S08LG32 Series Data Sheet, Rev. 7 16 Freescale Semiconductor
Electrical Characteristics
2.7
Supply Current Characteristics
Table 9. Supply Current Characteristics
This section includes information about power supply current in various operating modes.
Num 1
C C C C C P P C C
Parameter Run supply current FEI mode, all modules on
Symbol RIDD
Bus Freq 20 MHz
VDD (V) 3
Typ1 16.38
Max 27.85 28.05
Unit mA
Temp (C) -40 C to 85 C -40 C to105 C -40 C to 85 C -40 C to105 C
1 MHz
1.67
2.84 2.87
20 MHz
5
16.55
28.14 28.35
mA
-40 C to 85 C -40 C to105 C -40 C to 85 C -40 C to105 C
1 MHz
1.77
3.01 3.05
2
T T T T T T T T
Run supply current FEI mode, all modules off
RIDD
20 MHz
3
11.9
20.25 21.72
mA
-40 C to 85 C -40 C to105 C -40 C to 85 C -40 C to105 C
1 MHz
1.16
1.95 1.98
20 MHz
5
12.68
21.56 23.12
mA
-40 C to 85 C -40 C to105 C -40 C to 85 C -40 C to105 C
1 MHz
1.4
2.39 2.41
3
T T T T P P T T
Wait mode supply current FEI mode, all modules off
WIDD
20 MHz
3
7.9
13.42 13.59
mA
-40 C to 85 C -40 C to105 C -40 C to 85 C -40 C to105 C
1 MHz
0.88
1.49 1.51
20 MHz
5
8.13
13.81 13.98
mA
-40 C to 85 C -40 C to105 C -40 C to 85 C -40 C to105 C
1 MHz
1.12
1.91 1.94
4
C C P P
Stop2 mode supply current
S2IDD
n/a
3
1.1
16.0 39.0
A
-40 C to 85 C -40 C to105 C
5
1.2
18.7 46.1
A
-40 C to 85 C -40 C to105 C
5
C C P P
Stop3 mode supply current No clocks active
S3IDD
n/a
3
1.2
22.4 56.2
A
-40 C to 85 C -40 C to105 C
5
1.32
25.5 63.9
A
-40 C to 85 C -40 C to105 C
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 17
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Num 6 C T Parameter Stop2 adders: RTC using LPO RTC using low power crystal oscillator LCD2 with rbias (Low Gain) LCD2 with rbias (High Gain) LCD2 with Cpump RTC using LPO RTC using low power crystal oscillator LCD2 with rbias (Low Gain) LCD2 with rbias (High Gain) LCD2 with Cpump 7 T Stop3 adders: RTC using LPO RTC using low power crystal oscillator LCD2 with rbias (Low Gain) LCD2 with rbias (High Gain) LCD2 with Cpump RTC using LPO RTC using low power crystal oscillator LCD2 with rbias (Low Gain) LCD2 with rbias (High Gain) LCD2 with Cpump 5 -- n/a 3 5 Symbol -- Bus Freq n/a VDD (V) 3 Typ1 210 4.25 Max -- -- Unit nA A Temp (C) -40 C to 105 C
1.23 184 4.053 210 4.22
-- -- -- -- -- nA A -40 C to 85 C -40 C to 105 C
1.53 324 7.123 210 4.75
-- -- -- -- -- nA A -40 C to 85 C -40 C to 105 C
1.23 184 4.353 230 4.74
-- -- -- -- -- nA A -40 C to 85 C -40 C to 105 C
1.53 324 7.493
-- -- -- -40 C to 85 C
MC9S08LG32 Series Data Sheet, Rev. 7 18 Freescale Semiconductor
Electrical Characteristics
Table 9. Supply Current Characteristics (continued)
Num 8 C T Parameter Stop3 adders: EREFSTEN = 1 IREFSTEN = 1 LVD EREFSTEN = 1 IREFSTEN = 1 LVD Typical values are measured at 25 C. Characterized, not tested. LCD configured for Charge Pump Enabled VLL3 connected to VDD.. 3 This does not include current required for 32 kHz oscillator. 4 This is the maximum current when all LCD inputs/outputs are used.
1 2
Symbol --
Bus Freq n/a
VDD (V) 3
Typ1 4.58 71.7 94.35
Max -- -- -- -- -- --
Unit A
Temp (C) -40 C to 105 C
5
4.61 71.69 107.34
A
IDD
VDD
Figure 9. Typical Run IDD for FBE Mode at 1 MHz
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 19
Electrical Characteristics
IDD
VDD
Figure 10. Typical Run IDD for FBE Mode at 20 MHz
IDD
VDD
Figure 11. Typical Run IDD for FEE Mode at 1 MHz
MC9S08LG32 Series Data Sheet, Rev. 7 20 Freescale Semiconductor
Electrical Characteristics
IDD
VDD
Figure 12. Typical Run IDD for FEE Mode at 20 MHz
IDD
VDD
Figure 13. Typical Stop2 IDD
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 21
Electrical Characteristics
IDD
VDD
Figure 14. Typical Stop3 IDD
2.8
Num 1 C D
External Oscillator (XOSC) Characteristics
Table 10. Oscillator Electrical Specifications (Temperature Range = -40 C to 105 C Ambient)
Characteristic Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) * Low range (RANGE = 0) * High range (RANGE = 1) FEE or FBE mode2 * High range (RANGE = 1, HGO = 1) BLPE mode * High range (RANGE = 1, HGO = 0) BLPE mode Load capacitors Symbol flo fhi fhi-hgo fhi-lp C1 C2 Min 32 1 1 1 Typ1 -- -- -- -- Max 38.4 5 16 8 Unit kHz MHz MHz MHz
2
D
See crystal or resonator manufacturer's recommendation.
MC9S08LG32 Series Data Sheet, Rev. 7 22 Freescale Semiconductor
Electrical Characteristics
Table 10. Oscillator Electrical Specifications (Temperature Range = -40 C to 105 C Ambient) (continued)
Num 3 C D Characteristic Feedback resistor * Low range (32 kHz to 100 kHz) * High range (1 MHz to 16 MHz) Series resistor * Low range, low gain (RANGE = 0, HGO = 0) * Low range, high gain (RANGE = 0, HGO = 1) Series resistor * High range, low gain (RANGE = 1, HGO = 0) * High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz 6 T Crystal start-up time3, 4 * Low range (HGO = 0) * Low range (HGO = 1) * High range (HG0 = 0)5 * High range (HG0 = 1)5 Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) * FEE or FBE mode2 * BLPE mode tCSTL-LP tCSTL-HGO tCSTH-LP tCSTH-HGO fextal 0.03125 0 -- -- 5 40 Symbol RF -- -- RS 0 100 RS k 10 1 -- -- k Min Typ1 Max Unit M
4
D
5
D
-- -- -- -- -- -- --
0 0 0 500 3570 4 4
0 10 20 ms -- -- -- -- MHz
7
D
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 This parameter is characterized and not tested on each device. 4 Proper PC board layout procedures must be followed to achieve specifications. 5 4 MHz crystal
1 2
XOSC EXTAL XTAL RS
RF
C1
Crystal or Resonator C2
Figure 15. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 23
Electrical Characteristics
XOSC EXTAL XTAL
Crystal or Resonator
Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power
2.9
Num 1 2 3 4 C P C C P P 5 P P
Internal Clock Source (ICS) Characteristics
Table 11. ICS Frequency Specifications (Temperature Range = -40 C to 105 C Ambient)
Characteristic Average internal reference frequency -- factory trimmed at VDD = 5.0 V and temperature = 25 C Average internal reference frequency -- user trimmed Internal reference start-up time DCO output frequency range -- Low range (DRS = 00) trimmed2 Mid range (DRS = 01) DCO output Reference = 32768 Hz and DMX32 = 1 frequency2 Low range (DRS = 00) Mid range (DRS = 01) fdco_res_t fdco_res_t fdco_t fdco_t tAcquire CJitter Symbol fint_ft fint_t tIRST fdco_t Min -- 31.25 -- 16 32 fdco_DMX32 -- -- Typ1 32.768 -- 60 -- -- 19.92 39.85 0.1 0.2 -1.0 to +0.5 0.5 -- 0.02 Max -- 39.0625 100 20 40 -- -- 0.2 0.4 2 1 1 0.2 MHz Unit kHz kHz s MHz
6 7 8 9 10 11
1
C C C C C C
Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM)3 Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)3 Total deviation of trimmed DCO output frequency over voltage and temperature3 Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 C to 70 C3 FLL acquisition time3, 4 Long term jitter of DCO output clock (averaged over 2 ms interval)5
-- -- -- -- -- --
%fdco %fdco %fdco %fdco mS %fdco
2
Data in Typical column was characterized at 5.0 V, 25 C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This parameter is characterized and not tested on each device. 4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage for a given interval.
MC9S08LG32 Series Data Sheet, Rev. 7 24 Freescale Semiconductor
Electrical Characteristics
65.00 60.00 55.00 ICS Frequency (khz) 50.00 45.00 40.00 35.00 30.00 25.00 20.00
'0 00 0 '0 00 00 00 0 '0 11 00 01 1 '0 10 01 10 0 '0 01 01 11 1 '0 01 10 00 0 '0 00 10 01 0 '0 11 10 10 1 '0 10 11 11 0 '0 10 11 00 1 '1 01 00 01 0 '1 00 00 10 0 '1 11 00 11 1 '1 11 01 00 0 '1 10 01 01 1 '1 01 10 10 0 '1 00 10 11 1 '1 00 10 00 1 '1 11 11 01 0 '1 10 11 10 10 11 1
ICS Trim values -40C 25C 110C
Figure 17. Internal Oscillator Deviation from Trimmed Frequency
2.10
ADC Characteristics
Table 12. 12-bit ADC Operating Conditions
Conditions Absolute Delta to VDD (VDD - VDDAD)2 Symb VDDAD VDDAD VSSAD VREFH VREFL VADIN CADIN Min 2.7 -100 -100 -- -- VREFL -- Typ1 -- 0 0 -- -- -- 4.5 Max 5.5 +100 +100 -- -- VREFH 5.5 Unit V mV mV V V V pF Comment -- -- -- VREFH shorted to VDDAD VREFLshorted to VSSAD -- --
Characteristic Supply voltage
Ground voltage Ref Voltage High Ref Voltage Low Input Voltage Input Capacitance
Delta to VSS (VSS - VSSAD)2 -- -- -- --
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 25
Electrical Characteristics
Table 12. 12-bit ADC Operating Conditions (continued)
Characteristic Input Resistance Analog Source Resistance Conditions -- 12-bit mode fADCK > 4MHz fADCK < 4MHz 10-bit mode fADCK > 4MHz fADCK < 4MHz 8-bit mode (all valid fADCK) ADC Conversion Clock Freq.
1
Symb RADIN RAS
Min --
Typ1 5
Max 7
Unit k k
Comment -- External to MCU
-- -- -- -- -- fADCK 0.4 0.4
-- -- -- -- -- -- --
2 5 5 10 10 8.0 4.0 MHz --
High Speed (ADLPC = 0) Low Power (ADLPC = 1)
Typical values assume VDDAD = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference.
SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT ZAS RAS + VADIN - Pad leakage due to input protection
ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN
ADC SAR ENGINE
VAS
+ -
CAS
RADIN INPUT PIN
RADIN
INPUT PIN
RADIN CADIN
INPUT PIN
Figure 18. ADC Input Impedance Equivalency Diagram
MC9S08LG32 Series Data Sheet, Rev. 7 26 Freescale Semiconductor
Electrical Characteristics
Table 13. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD)
Num 1 C T Characteristic Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 Supply Current ADLPC = 1 ADLSMP = 0 ADCO = 1 Supply Current ADLPC = 0 ADLSMP = 1 ADCO = 1 Supply Current ADLPC = 0 ADLSMP = 0 ADCO = 1 Supply Current ADC Asynchronous Clock Source Conversion Time (Including sample time) Sample Time Conditions -- Symb IDDAD Min -- Typ1 195 Max -- Unit A Comment --
2
T
--
IDDAD
--
347
--
A
--
3
T
--
IDDAD
--
407
--
A
--
4
P
--
IDDAD
--
0.755
1
mA
--
5 6
-- P
Stop, Reset, Module Off High Speed (ADLPC=0) Low Power (ADLPC=1) Short sample (ADLSMP=0) Long sample (ADLSMP=1) Short sample (ADLSMP=0) Long sample (ADLSMP=1)
IDDAD fADACK 2 1.25 tADC -- -- tADS -- -- ETUE -- -- -- DNL -- -- -- INL -- -- -- EZS -- -- --
0.011 3.3 2 20 40 3.5 23.5 3.0 1 0.5 1.75 0.5 0.3 1.5 0.5 0.3 1.5 0.5 0.5
1 5 3.3 -- -- -- -- -- 2.5 1 -- 1.0 0.5 -- 1 0.5 -- 1.5 0.5
A MHz
-- tADACK = 1/fADACK See ADC chapter in the LG32 Reference Manual for conversion time variances Includes quantization
7
C
ADCK cycles ADCK cycles LSB2
8
C
9
T P T
Total Unadjusted Error
12-bit mode 10-bit mode 8-bit mode
10
T P T
Differential Non-Linearity
12-bit mode 10-bit mode3 8-bit mode3
LSB2
11
T P T
Integral Non-Linearity
12-bit mode 10-bit mode 8-bit mode
LSB2
12
T P T
Zero-Scale Error
12-bit mode 10-bit mode 8-bit mode
LSB2
VADIN = VSSAD
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 27
Electrical Characteristics
Table 13. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued)
Num 13 C T P T 14 D Quantization Error Characteristic Full-Scale Error Conditions 12-bit mode 10-bit mode 8-bit mode 12-bit mode 10-bit mode 8-bit mode 15 D Input Leakage Error 12-bit mode 10-bit mode 8-bit mode 16 C Temp Sensor Slope Temp Sensor Voltage -40 C to 25 C 25 C to 125C 25 C VTEMP25 m EIL EQ Symb EFS Min -- -- -- -- -- -- -- -- -- -- -- -- Typ1 1 0.5 0.5 -1 to 0 -- -- 1 0.2 0.1 1.646 1.769 701.2 Max -- 1 0.5 -- 0.5 0.5 -- 2.5 1 -- -- -- mV -- mV/C -- LSB2 Pad leakage4 * RAS LSB2 -- Unit LSB2 Comment VADIN = VDDAD
17
1
C
Typical values assume VDDAD = 5.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals.
MC9S08LG32 Series Data Sheet, Rev. 7 28 Freescale Semiconductor
Electrical Characteristics
2.11
AC Characteristics
This section describes timing characteristics for each peripheral system.
2.11.1
Num 1 2 3 4 5 6 7 C D D D D D D D
Control Timing
Table 14. Control Timing
Rating Bus frequency (tcyc = 1/fBus) Internal low power oscillator period External reset pulse width Reset low drive BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 IRQ pulse width Asynchronous path2 Synchronous path4 Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 Port rise and fall time -- (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1)
2
Symbol fBus tLPO textrst trstdrv tMSSU tMSH
Min dc 700 100 66 x tcyc 500 100
Typ1 -- -- -- -- -- --
Max 20 1300 -- -- -- --
Unit MHz s ns ns ns s ns
tILIH tIHIL tILIH tIHIL tRise tFall
100 1.5 x tcyc 100 1.5 x tcyc -- --
-- -- -- -- 3 30
-- -- ns -- -- ns -- --
8
D
9
C
1 2 3 4 5 6
Typical values are based on characterization data at VDD = 5.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 C to 105 C. Except for LCD pins in Open Drain mode.
textrst RESET PIN
Figure 19. Reset Timing
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 29
Electrical Characteristics
tIHIL IRQ/KBIPx
IRQ/KBIPx tILIH
Figure 20. IRQ/KBIPx Timing
2.11.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 15. TPM Input Timing
No. 1 2 3 4 5 C D D D D D Function External clock frequency External clock period External clock high time External clock low time Input capture pulse width Symbol fTCLK tTCLK tclkh tclkl tICPW Min 0 4 1.5 1.5 1.5 Max fBus/4 -- -- -- -- Unit Hz tcyc tcyc tcyc tcyc
tTCLK tclkh
TPMCLK tclkl
Figure 21. Timer External Clock
tICPW TPMCHn
TPMCHn tICPW
Figure 22. Timer Input Capture Pulse
MC9S08LG32 Series Data Sheet, Rev. 7 30 Freescale Semiconductor
Electrical Characteristics
2.11.3
SPI Timing
Table 16. SPI Timing
Table 16 and Figure 23 through Figure 26 describe the timing requirements for the SPI system.
No. --
C D
Function Operating frequency Master Slave SPSCK period Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SPSCK) high or low time Master Slave Data setup time (inputs) Master Slave Data hold time (inputs) Master Slave Slave access time Slave MISO disable time Data valid (after SPSCK edge) Master Slave Data hold time (outputs) Master Slave Rise time Input Output Fall time Input Output
Symbol fop
Min fBus/2048 0
Max fBus/2 fBus/4 2048 -- -- -- -- -- 1024 tcyc -- -- -- -- -- 1 1
Unit Hz
1
D
tSPSCK 2 4 tLead 1/2 1 tLag 1/2 1 tWSPSCK tcyc - 30 tcyc - 30 tSU 15 15 tHI 0 25 ta tdis tv -- -- tHO 0 0 tRI tRO tFI tFO -- -- -- -- -- -- tcyc - 25 25 tcyc - 25 25 ns ns ns ns ns ns 25 25 ns ns -- -- ns ns tcyc tcyc ns ns ns ns tSPSCK tcyc tSPSCK tcyc tcyc tcyc
2
D
3
D
4
D
5
D
6
D
7 8 9
D D D
10
D
11
D
12
D
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 31
Electrical Characteristics
SS1 (OUTPUT) 2 SPSCK (CPOL = 0) (OUTPUT) SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) MSB OUT2 6 MS BIN2 BIT 6 . . . 1 9 BIT 6 . . . 1 LSB OUT LSB IN 10 1 4 4 12 11 3
NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 23. SPI Master Timing (CPHA = 0)
SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 9 MOSI (OUTPUT) PORT DATA MASTER MSB OUT2 MSB IN2 6 BIT 6 . . . 1 10 BIT 6 . . . 1 MASTER LSB OUT PORT DATA LSB IN 4 11 12 12 11 3
NOTES:
1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 24. SPI Master Timing (CPHA =1)
MC9S08LG32 Series Data Sheet, Rev. 7 32 Freescale Semiconductor
Electrical Characteristics
SS (INPUT) 1 SPSCK (CPOL = 0) (INPUT) 2 SPSCK (CPOL = 1) (INPUT) 7 MISO (OUTPUT) SLAVE 5 MOSI (INPUT)
NOTE:
12
11
3
4
4
11
12 8
9 MSB OUT 6 MSB IN BIT 6 . . . 1 BIT 6 . . . 1
10
10
SEE NOTE 1
SLAVE LSB OUT
LSB IN
1. Not defined but normally MSB of character just received.
Figure 25. SPI Slave Timing (CPHA = 0)
SS (INPUT) 1 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) SEE NOTE 1 SLAVE 7 MOSI (INPUT) NOTE: o MSB IN MSB OUT 6 BIT 6 . . . 1 LSB IN 4 11 12 12 3 11
10 BIT 6 . . . 1 SLAVE LSB OUT
c
1. Not defined but normally LSB of character just received
Figure 26. SPI Slave Timing (CPHA = 1)
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 33
Electrical Characteristics
2.12
C D D D D D
LCD Specifications
Table 17. LCD Electricals, 3 V Glass
Characteristic VLL3 Supply Voltage LCD Frame Frequency LCD Charge Pump Capacitance LCD Bypass Capacitance LCD Glass Capacitance Symbol VLL3 fFrame CLCD CBYLCD Cglass Min 2.7 28 -- -- -- Typ -- 30 100 100 2000 Max 5.5 64 100 100 8000 Units V Hz pF
2.13
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 18. Flash Characteristics
C D D D D C C C C D D C C
1 2
Characteristic Supply voltage for program/erase -40 C to 85 C Supply voltage for read operation Internal FCLK frequency1
Symbol Vprog/erase VRead fFCLK tFcyc tprog tBurst tPage tMass RIDDBP RIDDPE
Min 2.7 2.7 150 5
Typical
Max 5.5 5.5 200 6.67
Unit V V kHz s tFcyc tFcyc tFcyc tFcyc
Internal FCLK period (1/FCLK) Byte program time (random location)2 Byte program time (burst Page erase time2 Mass erase time2 Byte program current3
3
9 4 4000 20,000 -- -- 10,000 4 6 -- 100,000 100 -- -- -- -- --
mode)2
mA mA cycles years
Page erase current
Program/erase endurance4 TL to TH = -40 C to + 85 C T = 25 C Data retention5 tD_ret
15
The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 5.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
MC9S08LG32 Series Data Sheet, Rev. 7 34 Freescale Semiconductor
Electrical Characteristics
2.14
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
2.14.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 19. Radiated Emissions, Electric Field
Parameter Radiated emissions, electric field Symbol VRE_TEM Conditions VDD = 5.5 TA = +25 oC Package type = 80 LQFP Frequency 0.15 - 50 MHz 50 - 150 MHz 150 - 500 MHz 500 - 1000 MHz IEC Level SAE Level
1
fOSC/fBUS 4 MHz crystal 16 MHz bus
Level1 (Max) 10 14 8 5 L 2
Unit dBV
-- --
Data based on qualification test results.
2.14.2
Conducted Transient Susceptibility
Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 20. Table 20. Conducted Susceptibility, EFT/B
Parameter Conducted susceptibility, electrical fast transient/burst (EFT/B) Symbol VCS_EFT Conditions fOSC/fBUS Result A B C D Amplitude1 (Min) >4.02 >4.03 >4.04 >4.0 Unit kV
4 kHz crystal VDD = 5.5 4 MHz bus TA = +25 oC Package type = 80-pin LQFP
1 2
Data based on qualification test results. Not tested in production. Exceptions as covered in footnotes 3 and 4.
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 35
Electrical Characteristics
3 4
Except pins PHT1, PTH2, PTH3, PTH4, PTH5. See figures below for values. Except pins PTF3, PTH5, PTH4, PHT0, Reset, and BKGD. See figures below for values.
Individual performance of each pin is shown in Figure 27, Figure 28, Figure 29, and Figure 30.
Figure 27. 4 MHz, Positive Polarity Pins 1 - 41
Note: RESET retested with 0.1 F capacitor from pin to ground is Class A compliant as shown by 48*.
Figure 28. 4 MHz, Positive Polarity Pins 42 - 80
MC9S08LG32 Series Data Sheet, Rev. 7 36 Freescale Semiconductor
Electrical Characteristics
Figure 29. 4 MHz, Negative Polarity Pins 1 - 41
Note: RESET retested with 0.1 F capacitor from pin to ground is Class A compliant as shown by 48*.
Figure 30. 4 MHz, Negative Polarity Pins 42 - 80
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 37
Ordering Information
The susceptibility performance classification is described in Table 21. Table 21. Susceptibility Performance Classification
Result A B No failure Self-recovering failure Soft failure Performance Criteria The MCU performs as designed during and after exposure. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation.
C
D
Hard failure
E
Damage
3
Ordering Information
Table 22. Device Numbering System
Device Number1 Memory Temperature Range (C) FLASH RAM Auto S9S08LG32J0CLK S9S08LG32J0CLH S9S08LG32J0CLF S9S08LG32J0VLK S9S08LG32J0VLH S9S08LG32J0VLF S9S08LG16J0VLH S9S08LG16J0VLF IMM MC9S08LG32CLK MC9S08LG32CLH MC9S08LG32CLF MC9S08LG16CLH MC9S08LG16CLF 18 KB 1984 32 KB 1984 -40 C to + 85 C Charge Pump 80-pin LQFP 64-pin LQFP 48-pin LQFP 64-pin LQFP 48-pin LQFP 18 KB 1984 32 KB 1984 -40 C to +105 C Register Bias 32 KB 1984 -40 C to +85 C Charge Pump 80-pin LQFP 64-pin LQFP 48-pin LQFP 80-pin LQFP 64-pin LQFP 48-pin LQFP 64-pin LQFP 48-pin LQFP LCD Mode Operation Available Packages2
This section contains ordering information for MC9S08LG32 and MC9S08LG16 devices.
See the MC9S08LG32 Reference Manual (document MC9S08LG32RM), for a complete description of modules included on each device. 2 See Table 23 for package information.
1
MC9S08LG32 Series Data Sheet, Rev. 7 38 Freescale Semiconductor
Package Information
3.1
Device Numbering System
S 9 S08 LG 32 J0 X XX Package designator (see Table 23) Temperature range (C = -40 C to 85 C) (V = -40 C to 105 C) Maskset Identifier Suffix (First digit usually references wafer fab Second digit usually differentiates mask rev) Approximate Flash size in KB
Example of the device numbering system:
Status/Partnumber Type (S = Maskset specific partnumber) Memory (9 = FLASH-based) Core Family
Figure 31. Device Number Example for Auto Parts
MC 9 S08 LG 32 Status (MC = Fully Qualified) Memory (9 = FLASH-based) Core Family C XX
Package designator (see Table 23) Temperature range (C = -40 C to 85 C) Approximate Flash size in KB
Figure 32. Device Number Example for IMM Parts
4
80 64 48
Package Information
Table 23. Package Descriptions
Pin Count Package Type Low Quad Flat Package Low Quad Flat Package Low Quad Flat Package Abbreviation LQFP LQFP LQFP Designator LK LH LF Case No. 917A 840F 932 Document No. 98ASS23237W 98ASS23234W 98ASH00962A
4.1
Mechanical Drawings
The following pages are mechanical drawings for the packages described in Table 23. For the latest available drawings please visit our web site (http://www.freescale.com) and enter the package's document number into the keyword search box.
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 39
Package Information
4.1.1
80-pin LQFP
MC9S08LG32 Series Data Sheet, Rev. 7 40 Freescale Semiconductor
Package Information
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 41
Package Information
Figure 33. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W)
MC9S08LG32 Series Data Sheet, Rev. 7 42 Freescale Semiconductor
Package Information
4.1.2
64-pin LQFP
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 43
Package Information
MC9S08LG32 Series Data Sheet, Rev. 7 44 Freescale Semiconductor
Package Information
Figure 34. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W)
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 45
Package Information
4.1.3
48-pin LQFP
MC9S08LG32 Series Data Sheet, Rev. 7 46 Freescale Semiconductor
Package Information
Figure 35. 48-pin LQFP Package Drawing (Case 932, Doc #98ASH00962A)
MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 47
Revision History
5
Revision History
http://www.freescale.com
To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: The following revision history table summarizes changes contained in this document. Table 24. Revision History
Revision 1 2 3 4 5 6 7 Date 8/2008 9/2008 11/2008 2/2009 4/2009 4/2009 8/2009 First Initial release. Second Initial Release. Alpha Customer Release. Launch Release. Added EMC Radiated Emission and Transient Susceptibility data in Table 19 and Table 20. Updated EMC performance data. Updated auto part numbers, changed TCLK, T0CH0, T0CH1, T1CH0, T1CH1, T1CH2, T1CH3, T1CH3, T1CH4, and T1CH5 to TPMCLK, TPM0CH0, TPM0CH1,TPM1CH0, TPM1CH1, TPM1CH2, TPM1CH3, TPM1CH4, and TPM1CH5, and changed the maximum LCD frame frequency to 64 Hz. Description of Changes
MC9S08LG32 Series Data Sheet, Rev. 7 48 Freescale Semiconductor
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MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 49
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Document Number: MC9S08LG32
Rev. 7 8/2009

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